Electronic News took its roundtable format to the Fabless Semiconductor Association's Suppliers Expo late yesterday afternoon to discuss design for manufacturing and whether it works. Panelists were Di Ma, VP of field technical support at TSMC North America; William Hata, VP of product engineering at Altera; Mark Templeton, president and chief strategy officer at ARM; and Joseph Sawicki, VP and general manager of Mentor Graphics' design to silicon division. What follows are excerpts of that conversation, which was recorded in front of a live audience.
Ma: Traditionally, whenever you did less-advanced technology, the yield was limited to defect density inside a fab. If you have a design that follows the typical design rules, we can predict very well the yield based upon the manufacturing defect density. With more advanced technology, the situation has changed. There are other defects that hurt yield and which cannot be completely caught by design rules. Those variants cause the design to not yield to its optimum level. That's what design for manufacturing is about.
Templeton: A lot of people focus on the physical or layout aspects of design for manufacturing and somehow parallel it to what we used to think of as design rules. In our business we've found that transistors don't behave like they used to. It's very hard to predict with any accuracy what a transistor is going to do. You have a much wider dynamic range with regard to the performance. Not only do we have to worry about verifying the layout and the behavior of the transistor, but we have to re-architect building blocks so they are much more tolerant of these wide variations. So DFM isn't just about the physical layout or the optics, it's about the transistor design or even the architecture at the circuit level so that you do have robust designs long before you even get to layout.
Sawicki: If you look at DFM, the main meaning today is design for marketing. Everyone wants to talk about DFM, and this drives the excitement level. There are two waves. The first is almost entirely about doing OPC [optical proximity correction] at the foundry. The good news is that we wouldn't have to have any of these arguments about what is DFM if that didn't work. You wouldn't have a 90 nanometer or 65 nanometer node. Most of the stuff coming up now is about a ubiquitous and pervasive driving of variability into the design process, whether that involves shape formation that is more mask-centric, or variability about transistor behavior. It's not going to be all that easy to do width- and length-based design rules anymore.
Hata: The first generation for DFM was just the post-processing. You would finish your design and then it would be the OPC and data processing that would occur to make the yield better and to improve the cost structure of the product. DFM is all the techniques that are used -- the rules and different methodologies -- so that you can build those into the design methods, reduce the cost and improve the availability of the product. It goes beyond the function to ensure the total product requirements.
Sawicki: For it to work, it has to be collaborative. If you're in a situation where you start pointing fingers, something else is going on. The reality is, if you're at the cutting edge of a process, it is hard. It's hard for the manufacturer, it's hard for the designer, and some of the effects you're going to face are not well understood by either. It does take a lot of cooperation and collaboration. At the end of the day, you need to run some silicon to get it right.
Hata: I think that really gets to the heart of the problem. It is a collaboration. It's an intersection between the manufacturing methods, the foundries and the mask making shops and the design methods. Previously, they were separate. Now they have to work together. You have to be able to pass the information back and forth between what rules and what techniques are difficult to execute from the design perspective, and what rules are very important from the manufacturing standpoint. Maybe they're theoretically possible, but by pushing the rules that hard that small incremental change is what can really make a difference in the cost structure.
Sawicki: I think collaboration is also interesting when you consider what EDA does. When I was working on a physical verification tool, 180 (nanometers) would roll in and the first couple of rule decks would go out, and the phone calls would start coming in saying, ‘We need the rules to work this way.' We're well at the back end of the dog. Today the vast majority of researchers in my group are working on 45 nanometers. That's a node we're not even coming close to. The collaboration has radically changed the amount of time we spend on initial process development.
Ma: We believe that collaboration is a key element, but TSMC has taken very strong ownership in working with customers and third-party IP providers to come up with solutions for our joint customers. I don't know whose responsibility that is, but TSMC is taking strong ownership.
Electronic News: But is there really communication between these groups? Some of the process data that resides in the foundries is not being shared with companies that build their chips there.
Templeton: It's not ubiquitous. There's some fairly healthy conversation going on right now about what data needs to be shared. One thing you've got to be careful about is people have talked in the past about how they want to have the OPC. A 200 million transistor chip running through OPC for a poly layer will probably take 128 CPUs three days. Do you have those compute resources and do you want to do that? Last week we were in a meeting with a foundry, a fabless customer and ourselves and talking about how we could take that sort of data and make it useful for a designer and how you could use that going forward. The conversations have taken place and we're going to be ready for mid-65 or more importantly 45 [nanometers].
Hata: The communication and collaboration is difficult, particularly with fabless companies. With an integrated IDM, you would think inherently there is better communication between a manufacturing organization and design organization because supposedly they have the same goal of making the companies successful. The general structure of the new supply chain, where we segment it into so many pieces and subcontract from chip design to foundry to back-end services naturally moves some of these companies apart. Those that are most successful try to break down those barriers and create a collaborative and cooperative environment, which is necessary if you want to execute on those plans.
Templeton: If you go back and compare the fabless model to the vertical companies, they had their own process and sold chips, but they were really evaluated on their chips and not the process technology. But if you're a pure-play foundry, your marketing tool is your process spec. One thing that you don't want to do early in a product lifecycle is put out a process spec that looks like it has real issues. You don't want to say we have DFM over here because we don't know how to manufacture it well. Early in the process, many foundries don't know what's going to be solid and what they're going to fix later, what a designer will have to deal with and what problems will go away in a year. Some foundries are very good at developing trust and being very open with that information. Others may not be. The ones that are more communicative will do better over time.
Ma: It depends on how closely the fabless company and the foundry can work together. Certainly, a foundry's success is dependent upon its customers' success. There's a very strong motivation on the foundry's side to enable the customers to be successful. There's a strong motivation for TSMC to work with customers on a collaborative basis. We do believe this collaboration is very important. Remember, the foundry is also learning as we go, so trust is important. If customers come back and say our data is not accurate, it will make customers less willing to share data. Without good data, the customer cannot be successful.
Hata: To a certain degree, that level of trust was always necessary but perhaps we didn't see it. While it was possible to manufacture a product and bring it to market with a less collaborative process, you used more generic processes and design rules and created a product that was differentiated only in the IP. But that was without the capability of the supply chain. The difference today is that we have the requirement to manufacture the product with the right yield and cost structure and we need to make money. To get enough profit out of the product we build we need to leverage the entire development cycle from the IP that's in the silicon to the software and not leave anything on the table.
Sawicki: The first generation of DFM tools exist or we wouldn't be having this conversation. The second generation is really early. You'll be able to tell when the tools are there because DFM will stop being so much of a buzzword. What we're talking about is more yield grading tools. We'll be talking about tools that do variability analysis on timing and tools that do printability analysis that feed into timing analysis on cells. There's no such thing as a DFM tool that will solve all your problems. We're not in the router space, but I guarantee you routers are going to get a lot more DFM-friendly than they are today. There's going to be a lot of other adjunct tools that are in the flow.
Hata: There isn't a tool today and perhaps there never will be a single tool. There is a collection of tools and techniques. Some of them are just plain architecture -- decisions that are made as you are defining what that product looks like and how to marry the design and the production side together. It's not any specific hard and fast rule that can be coded into a system to produce the right answer.
Templeton: As we take this down to the circuit design level, there really is an absence of tools. Now we need tools that give us statistical design techniques at the circuit level. If you look at analog design, this is critical. Quite often your worst-case corner isn't the process, it's some weird blend of things. If you change one transistor and not only does the design change, that corner moves. And the tools to analyze that are coming.
Sawicki: Everyone who has a full flow says you need a full flow. Those of us who don't have a full flow say you need best-in-class tools. I'm not sure what's changed that one company can provide enough expertise in every tool to provide a single flow.
Templeton: We've thought historically of tools as an algorithm that someone codes up that you can run something on. To solve the DFM problem, it's not just an algorithm and a tool. It's a deep knowledge of the domain. That is a change for EDA.
Sawicki: It's impossible to eliminate defects. Even with the aspect of particle-defect driven yield versus the systematic issues that have to do with printability, this problem is not getting any easier. You're getting less defect density in the foundry but feature sizes are getting so small that it's hard to drive that down to a minimal level.
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